FPGA Firmware Engineer

About the role

About Singular Photonics: Singular Photonics is a fast-growing fabless semiconductor start-up, developing Single-Photon Avalanche Diode (SPAD) sensors that bring advanced computation directly into imaging. Our sensors enable innovations across LiDAR, fluorescence lifetime imaging (FLIM), spectroscopy and time-resolved optical measurements, powering next-generation solutions for customers worldwide. Based at Orchard Brae House in Edinburgh, we are a close-knit team at the forefront of the photonics revolution. About the Role: We are seeking an FPGA Firmware Engineer to join our multidisciplinary R&D team. This is an FPGA role: you will design, implement and verify the Verilog firmware that powers our SPAD sensors, captures photon timing data at high rates and streams it to the host. Our sensors generate data faster than most imaging systems ever see, so the interesting problems here are real ones: clock domain crossing, timing closure and getting data off the device without losing a photon. You will work alongside our hardware, ASIC and software engineers, from architecture through to system bring-up and customer deployment. You will report to the Lead Firmware Engineer. Key Responsibilities: Architecture: Define FPGA requirements and architecture for SPAD sensor readout, in discussion with the hardware, ASIC and software teams. RTL Design: Implement, verify and debug Verilog modules for data acquisition, photon timing, histogramming and sensor control. Verification: Design and run simulations and testbenches, with coverage sufficient to trust the design before it reaches hardware. Synthesis & Timing: Own synthesis, constraints, clock domain crossing and timing closure on AMD-Xilinx FPGA family devices in Vivado. High-Speed Interfaces: Build and integrate the high-speed interfaces that move sensor data: PCIe, USB3, Ethernet, AXI interface, MIPI, LVDS, SLVS, Camera Link. Bring-Up & Debug: Lead firmware bring-up on new boards and sensors, debugging with oscilloscopes, logic analysers and in-system probes. Source Control & Build: Keep RTL under version control with a repeatable, automated build, and document designs to the standard our ISO 9001 design control process requires. Reviews & Support: Contribute to design reviews, and support the software team and customers during field integration. Experience & Skills: Essential: Strong proficiency in Verilog, and a solid grounding in RTL design, synthesis and timing closure. Hands-on experience with AMD-Xilinx Vivado and its toolchain. Experience writing your own testbenches and verifying a design in simulation before hardware. Experience bringing up firmware on real hardware and debugging it in the lab. Experience with at least one high-speed interface or bus at RTL level. Comfortable in a small company where priorities shift and everyone pitches in. Working with complex, existing codebases and seamlessly integrating new functionality with minimal disruption. Desirable: SystemVerilog, and verification practices beyond directed testbenches. Comfortable working in Linux operating systems. Exposure to any of PCIe, AXI interface, USB3, Ethernet, MIPI, LVDS, SLVS or Camera Link. C, C++ or Python for embedded software integration and test automation. Experience with image sensors, time-of-flight, TDCs or single-photon detection. Familiarity with PCB design tools such as Altium Designer, and reading schematics during debug. Educational Background: Degree in Electronics Engineering or a related field, or equivalent practical experience. 2-5 years' experience in FPGA and digital design. Key Attributes & Behaviours: Rigour: Disciplined about verification - you would rather find it in simulation than on the bench. Debugging: Systematic when the fault could be in the RTL, the board or the sensor, and comfortable with the instruments that tell you which. Clarity: Writes documentation and code that colleagues can pick up without you in the room. Collaboration: Works well across the hardware, ASIC

Skills